1. Field of the Invention
The present invention relates to a memory controller for controlling a dynamic random access memory (“DRAM”).
2. Description of the Background Art
For an electronic device such as a digital still camera, a DRAM has been conventionally employed as a memory IC. In a DRAM, capacitors for storing data are provided respectively for memory cells. Because of a simpler structure of a DRAM as compared to a structure of a static random access memory (“SRAM”) or the like, an integration density thereof can be easily increased on one hand. However, on the other hand, as electric charges in capacitors decrease with time, a burden of periodically performing a refresh operation for injecting electric charges into memory cells is caused. During a refresh operation, a data transfer with a DRAM such as writing of data and readout of data cannot be accomplished.
In the meantime, recent electronic devices are required to process huge volumes of data such as images in real time. Thus, also a DRAM for storing data which is to be processed is required to transfer huge volumes of data at an extremely high speed.
However, it is necessary to periodically perform a refresh operation of a DRAM. According to the conventional arts, when a necessity of a data transfer and a necessity of a refresh operation arise at the same time, a refresh operation is preferentially performed, so that a data transfer is suspended. Occurrence of such a situation in which a data transfer is suspended in order to preferentially perform a refresh operation probably lowers an effective band of a bus (an efficiency in a data transfer on a bus), leading to reduction of a processing speed of an entire processing system.